Generally, a MOSFET is a field effect transistor, in which gate electrodes formed on top of a semiconductor substrate are isolated by a thin insulating film, and is a semiconductor device having characteristics suitable for high-density integration without a decrease in impedance unlike a junction type transistor.
However, as the integration degree of a semiconductor device increases, the size of the device is reduced. Thus, the threshold voltage of a transistor decreases, to bring about a short channel effect or deepen the INWE (inverse narrow width effect) by the edges of the active regions in a shallow trench isolation process. Accordingly, a leakage current characteristic is observed in subthreshold regions and off regions of the MOSFET, and the characteristics of the semiconductor device, for example, the refresh time or data retention time of a DRAM is degraded.
Recently, a recessed gate MOSFET has developed, which is able to suppress a decrease in the threshold voltage by increasing the channel length without increasing the doping concentration of a semiconductor device. A method for manufacturing a recessed gate MOSFET has increased the channel length in a vertical direction by recessing a semiconductor substrate, where channel regions are to be formed, at a predetermined depth, and forming gate electrodes on the recessed substrate. In other words, since an effective channel length is increased just as much as the semiconductor substrate is recessed, it is possible to obtain a short channel margin without increasing the doping concentration of the channel regions, which prevents the degradation of the characteristics such as the refresh time, data retention time, etc. of a DRAM.
FIGS. 1a and 1b are vertical cross sectional views showing a recessed gate MOSFET structure in the conventional art.
Referring to FIG. 1a, in the conventional MOSFET, device isolation films 12 of a STI structure are formed on a silicon substrate as a semiconductor substrate 10, recessed gate electrodes 16 and 18 formed by gap-filling through a gate insulating film 14 in the recess regions of the substrate 10 between the device isolation films 12 that are etched at a predetermined depth, and spacers 22 made of insulating material are formed on the side walls of the gate electrodes 16 and 18. At this point, the lower gate electrode 16 is formed of doped polysilicon, and the upper gate electrode 18 is formed of metal or metal silicide. A hard mask 20 of insulating material, for instance, SiON, is additionally formed on top of the gate electrode.
Further, source/drain regions 24 ion-implanted with a n-type or p-type dopant are formed in the semiconductor substrate 10 exposed between the spacers 22, and spacers 26 made of insulating material are formed on side walls of the hard mask 20 and gate electrodes 16 and 18.
Besides, gap-filled contacts 28 are formed in shallow etched grooves of the semiconductor substrate 10 exposed between the spacers 26 and in spaces formed there between.
The recessed gate MOSFET thus constructed in the conventional art can solve the above problem caused from the short channel effect since the width of the gate electrodes 16 in the recessed regions is greater than the width of the gate electrodes 18 at the upper parts to thus increase the channel length as compared to a typical MOSFET of a planar structure. However, as the overlap between the gate electrode 16 and 18 and the source/drain regions 24 is increased (b), GIDL (gate induce drain leakage) is increased, or as the stress max point and an electron field max point are consistent (a) at recessed gate edges, leakage current is abnormally increased, and so on. Consequently, in a DRAM having this recessed gate MOSFET, refresh time or data detention time or the like is reduced as before.
To overcome this problem, an outer gate structure may be made by reducing the width of the recessed gate electrode 16 and broadening source/drain regions. But, it is very difficult to define recessed gate regions with a decreased width and then etching them.